====== Make Files ======

This is a good tutorial on make files [[http://www.physics.utah.edu/~p5720/rsrc/make.html|link]].

If the code is self contained you can run your program with:
<code bash>
gcc prog.c -o prog
</code>

If you want to do more complicated stuff the compile command will get much more
complicated.

Solution is to use a make utility (or... use [[CMake]] :)

<code make>
# This is a makefile.
CC=gcc
CFLAGS=-Wall
LDFLAGS=-lm

myprog: myprog.o more_code.o
	${CC} ${CFLAGS} myprog.o more_code.o ${LDFLAGS} -o myprog
   
clean: 
  \rm myprog.o more_code.o myprog
</code>
  
The make specific variables are in capital letters and they follow a convention such
that: 
    * ''%%CC%%'' refers to the compiler
    * ''%%CFLAGS%%'' contains compiler directives/options
    * ''%%LDFLAGS%%'' is a list of link (or "load") directives.
    * note there is a tab before ''%%${CC}%%''

The cool thing about make is that it will only compile stuff that has changed since
the last time it was ran.

You can have multiple targets in a make file!

The general run down of a make file looks like this:

<code make>
vars = values

target: dependencies
    command-list

targ2: more dependencies
    another-command-list
</code>
    
When you run make it opens up Makefile and seeks out the target name if it was
specified. If it was not, it runs the first target.

In the end you get a command that says: 

<code bash>
Compiler CFLAGS myprog.c LDFLAGS myprog
</code>

**Ps. Use [[CMake]] :)**